Dr. John M. Andrews
Adjunct Professor, Department of Physics

Education

B.S. Physics and Mathematics, Magna Cum Laude, Houghton College, Houghton, NY

Ph.D. Physics, Massachusetts Institute of Technology (MIT), Cambridge, MA

Professional Experience

1996-2000 Member, Allegany County Economic Development Zone Administrative Board; Adjunct Professor of Electrical Engineering, and Computer Science, George Washington University

1992-2000 Chief Scientist, Nantron Associates, LLC, Watchung, NJ; Charter Member, IEEE NCAC Consultants Network

1990-1992 Section Head, Naval Research Laboratory, Washington, DC

1983-1989 Distinguished Member of Technical Staff, AT&T Bell Labs, Murray Hill, NJ

1966-1982 Member of Technical Staff, AT&T Bell Labs, Murray Hill, NJ and Allentown, PA

1964-1966 Research Associate, Research Laboratory of Electronics, MIT, Cambridge, MA; Consultant, Sanders Associates, Nashua, NH

Induction as fellow of the IEEE (Institute of Electrical and Electronic Engineers) in Millburn, NJ in 1987.

Research

• Carried out pioneering research on silicides for integrated circuit contacts
This work was cited by the IEEE and led to a Fellow Award.
 
• Invented an advanced design for a palladium target for X-ray lithography capable of 0.25-micron line widths.
 
• Developed revolutionary stepped-field method for determining dielectric
breakdown in thin insulating films.
 
• Developed automated electrical evaluation of E-beam direct-write patterns.
Demonstrated performance from 1 micron to 0.05 microns.

Manufacturing

• Solved numerous manufacturing problems working with AT&T Technology Systems engineers in Allentown, PA.
 
• Introduced platinum silicide Schottky diodes into manufacture for improved bipolar transistor performance.
 
• Evaluated manufacturing issues for electrically programmable read-only-memories. Developed acceptance criteria for read-write performance.
 
• Developed an intrinsic gettering process for sub-micron ULSI circuit manufacture.

Processing

• CMOS Process Engineer for AT&T, responsible for processing high-speed
integrated circuits. Attained world speed record for a CMOS circuit in 1988.

Reliability

• Device Characterization, Accelerated Ageing, Failure Mode Analysis, Nantron Associates.

Supervision

• Head, Advanced Processing Section in the Nanoelectronics Processing Facility at the Naval Research Laboratory, Washington, DC.

Contracts

• Contract monitor for the National X-Ray Program

Teaching Experience

2004 Department of Physics and Earth Science
Houghton College, Houghton, NY

2001 Department of Physics
NJIT, Newark, NJ

1997-1999 Department of Electrical Engineering and Computer Science
George Washington University, Washington, DC

1997 Department of Physics
George Mason University, Fairfax, VA

Department of Electrical Engineering and Computer Science
George Mason University, Fairfax, VA

Department of Physics
Northern Virginia Community College, Alexandria, VA

1995-1996 Department of Physics, Houghton College, Houghton, NY

1994 Department of Electrical Engineering and Computer Science
Virginia Polytechnic Institute, Blacksburg, VA

Department of Electrical Engineering Technology
Alfred State University, Alfred, NY

1993 Department of Electrical Engineering and Computer Science
George Mason University, Fairfax, VA

1990-1991 Department of Electrical Engineering and Computer Science
University of Maryland, College Park, MD

1989 Department of Electrical Engineering and Computer Science
The Johns Hopkins University, Baltimore, MD

1988 Department of Electrical Engineering and Computer Science
Rutgers University, Piscataway, NJ

Department of Electrical Engineering and Computer Science
Stevens Institute of Technology, Hoboken, NJ

Patents of Dr. John M. Andrews

1. “Control Circuit for Insulated Gate Field Effect Transistors,” Patent No. 3,665,218, issued May 23, 1972.

2. “Solid State Temperature Sensor Employing a Pair of Dissimilar Schottky-Barrier Diodes,” Patent No. 3,719,797, issued March 6, 1973.

3. “Schottky Barrier Diode Contacts,” Patent No. 3,964,084, issued June 15, 1976.

4. “Fabrication of Palladium Anode for X-Ray Lithography,” Patent No. 4,319,967, issued March 16, 1982.

5. “A Method of Manufacturing Semiconductor Devices Involving the Detection of Water,” filed August 18, 1989.

6. “Method of Fabricating Semiconductor Devices Involving the Detection of Impurities,” filed November 7, 1989.

7. “Article Comprising a High Value Resistor,” filed June 19, 1990.

Publications

1. “Thermal Microwave Phonons,” by J. M. Andrews, Jr., and M. W. P. Strandberg, Proc. IEEE 54, 523-528 (1966).

2. “Bolometric Detection of Coherent 9-GHz Longitudinal Phonons in X-Cut Quartz,” by John M. Andrews, Jr., and M. W. P. Strandberg, J. Appl. Phys. 38, 2660-2662 (1967).

3. “Effect of Phonon Dispersion on Heat-Pulse Shape,” by J. M. Andrews, Jr., and M. W. P. Strandberg, Phys. Rev. 172, 869-872 (1968).

4. “Ohmic Contacts to Silicon,” by M. P. Lepselter and J. M. Andrews, Ohmic Contacts to Semiconductors, pp. 159-186, B. Schwartz, ed., Electrochem. Soc., Pennington, NJ (1969).

5. “Reverse Current-Voltage Characteristics of Metal-Silicide Schottky Diodes,” by J. M. Andrews and M. P. Lepselter, Solid-St. Electron. 13, 1011-1023 (1970).

6. “Formation of NiSi and Current Transport Across the NiSi-Si Interface,” by J. M. Andrews and F. B. Koch, Bull. Am. Phys. Soc. 15, 1327 (1970).

7. “Formation of NiSi and Current Transport across the NiSi-Si Interface,” by J. M. Andrews and F. B. Koch, Solid-St. Electron. 14, 901-908 (1971).

8. “Electrochemical Charging of Thermal SiO2 Films by Injected Electron Currents,” by E. H. Nicollian, C. N. Berglund, P. F. Schmidt, and J. M. Andrews, J. Appl. Phys. 42, 5654-5664 (1971).

9. “Electrical Charge Storage in Irradiated Insulating Films,” by J. M. Andrews and J. P. Mitchell, Eighth Annual Proceedings: Reliability Physics, Las Vegas, NV, Apr. 7-10, 1970, pp. 247-255, J. B. Morris, ed., IEEE, New York, NY (1971).

10. “Fowler-Nordheim Tunneling at a Metal-Semiconductor Interface,” by J. M. Andrews, Bull. Am. Phys. Soc. 16, 840 (1971).

11. “The Role of the Metal-Semiconductor Interface in Silicon Integrated Circuit Technology,” by J. M. Andrews, Proc. Symposium on Electronic and Structural Properties of Interfaces, pp. S42-S54, T. J. DiStefano and T. C. McGill, eds., American Vacuum Society, American Institute of Physics, New York, NY (1974).

12. “The Role of the Metal-Semiconductor Interface in Silicon Integrated Circuit Technology,” by J. M. Andrews, J. Vac. Sci. Technol. 11, 972-984 (1974).

13. “Chemical Bonding and Structure of Metal-Semiconductor Interfaces,” by J. M. Andrews and J. C. Phillips, Phys. Rev. Lett. 35, 56-59 (1975).

14. “Schottky Barriers and Interfacial Chemistry,” by J. M. Andrews, Abs. No. 191, p. 452, The Electrochemical Society Extended Abstracts, Spring Meeting, Toronto, Ont., Can. (1975).

15. “Detection of Al and Mg Contamination in Sputtered Pt Films by Auger Electron Spectroscopy,” by J. M. Andrews and J. M. Morabito, Abs. 191, p. 174, The Electrochemical Society Extended Abstracts, Spring Meeting, Toronto, Ont., Can. (1975).

16. “Chemical Bonding and Structure of Metal-Semiconductor Interfaces,” by J. M. Andrews and J. C. Phillips, CRC Critical Reviews in Solid State Sciences 5, 405-408 (1975).

17. “Detection of Al and Mg Contamination in Sputtered Pt Films by Auger Electron Spectroscopy,” by J. M. Andrews and J. M. Morabito, Thin Solid Films 37, 357-372 (1976).

18. “Electrical Conduction in Implanted Polycrystalline Silicon,” by J. M. Andrews, J. Electron. Mater. 8, 227-247 (1979).

19. “High-Field Dark Currents in Thin CVD Silicon Nitride with Graded Interfacial Composition,” by J. M. Andrews, B. G. Jackson, and W. J. Polito, Appl. Phys Lett. 34, 785-787 (1979).

20. “High-Field Dark Currents in Thin CVD Silicon Nitride,” by J. M. Andrews, B. G. Jackson, and W. J. Polito, J. Appl. Phys. 51, 495-502 (1980).

21. “Detection of Sputter Contamination and Sputter-Etch Residue by Ion Microprobe Analysis,” by J. M. Andrews, L. E. Katz, and J. W. Colby, Thin Solid Films 67, 325-340 (1980).

22. “Oxygen Precipitation, Denuded Zone Formation, and Wafer Warpage in CZ Silicon with Very High Interstitial Oxygen Content,” by J. M. Andrews, C. A. Clark, S. Muller, and G. A. Rozgonyi, Proc. First International Symposium on VLSI Science and Technology PV 82-7, pp. 43-52, C. J. Dell’Oca and W. Murray Bullis, eds., Electrochem. Soc., Pennington, NJ (1982).

23. “Gettering at Lower Temperatures by Phosphorus Diffusion and Back Surface Damage,” by J. M. Andrews, P. A. Heimann, and R. A. Kushner, Proc. First International Symposium on VLSI Science and Technology PV 82-7, pp. 68-75, C. J. Dell’Oca and W. Murray Bullis, eds., Electrochem. Soc., Pennington, NJ (1982).

24. “Electromigration Induced Shallow Junction Leakage with Al/Poly-Si Metallization,” by S. Vaidya, A. K. Sinha, and J. M. Andrews, J. Electrochem. Soc. 130, 496-501 (1983).

25. “A Lithographic Mask System for MOS Fine-Line Process Development,” by J. M. Andrews, Bell Syst. Tech. J. 62, 1107-1160 (1983).

26. “Oxygen Out-Diffusion Model for Denuded Zone Formation in Czochralski-Grown Silicon with High Intersitital Oxygen Content,” by John Andrews, Proc. Symposium on Defects in Silicon, pp. 133-141, W. Murray Bullis and L. C. Kimerling, eds., Electrochem. Soc., Pennington, NJ (1983).

27. “High Temperature Stability of PtSi Formed by Reaction of Metal with Silicon or by Cosputtering,” by S. P. Murarka, E. Kinsbron, D. B. Fraser, J. M. Andrews, and E. J. Lloyd, J. Appl. Phys. 54, 6943-6951 (1983).

28. “Intrinsic Gettering of Shallow p-n Junctions by Oxygen Precipitates in Czochralski-Grown Silicon,” by John Andrews, Proc. Symposium on Reduced Temperature Processing for VLSI PV 86-5, pp. 387-399, R. Reif and G. R. Srinivasan, eds., Electrochem. Soc., Pennington, NJ (1986).

29. “Gettering Processes for Sub-Micron VLSI,” by John Andrews, Proc. International Conference on Semiconductor and Integrated Circuit Technology, pp. 114-116, W. Xiuying and M. Bangxian, eds., World Scientific Pub. Co., Ltd., Singapore (1986).

30. “Quantitative Analysis of Oxygen in Thermally-Annealed Czochralski-Grown Silicon by Room Temperature Infrared Spectroscopy,” by L. Seibles and J. M. Andrews, The Materials Research Society Abstracts, 1986 Fall Meeting, Boston, MA, Abs. No. CP.5, p. 127, Materials Research Society, Pittsburgh, PA (1986).

31. “Gettering Processes for Sub-Micron VLSI,” by John Andrews, Science and Technology of Microfabrication, R. E. Howard, E. L. Hu, S. Pang, and S. Namba, eds., p. 289, Materials Research Society, Pittsburgh, PA (1987).

32. “Dielectric Breakdown Strength of LPCVD SiO2 Deposited at 500 �C,” by John Andrews and Gerald Smolinsky, Proc. Tenth International Conference on Chemical Vapor Deposition PV 87-8, pp. 497-507, G. W. Cullen, ed., Electrochem. Soc., Pennington, NJ (1987).

33. “A 2-GHz CMOS Dual-Modulus Prescaler IC,” by H.-I. Cong, J. M. Andrews, D. M. Boulin, S.-C. Fang, S. J. Hillenius, and J. A. Michejda, Proc. International Solid-St. Circuits Conference, Abs. No. THAM 11.1, p. 138, San Francisco, CA (1988).

34. “Multigigahertz CMOS Dual-Modulus Prescaler IC,” by H.-I. Cong, J. M. Andrews, D. M. Boulin, S.-C. Fang, S. J. Hillenius, and J. A. Michejda, IEEE J. Solid-St. Circuits SC-23, 1189-1194 (1988).

35. “A 6.75 ns Single Level Metal CMOS 16x16 Multiplier IC,” by R. Sharma, A. D. Lopez, J. A. Michejda, S. J. Hillenius, J. M. Andrews, and A. J. Studwell, Proc. 1988 Symposium on VLSI Circuits, Abs. No. VIII-3, pp. 91-92 (1988).

36. “A 6.75 ns 16x16-Bit Multiplier in Single-Level Metal CMOS Technology,” by R. Sharma, A. D. Lopez, J. A. Michejda, S. J. Hillenius, J. M. Andrews, and A. J. Studwell, IEEE J. Solid-St. Circuits SC-24, 922-927 (1989).

37. “Electrical Behavior of Spin-On Silicon Dioxide (SOX) in a Metal-Semiconductor Structure,” by N. Lifshitz, G. Smolinsky, and J. M. Andrews, Chemical Perspectives of Microelectronic Materials, M. E. Gross, J. T. Yates, and J. Jasinski, eds., MRS Proc. 161, pp. 575-580, Materials Research Society, Pittsburgh, PA (1989).

38. “Mobile Charge in a Novel Spin-On Oxide (SOX): Detection of Hydrogen in Dielectrics,” by N. Lifshitz, G. Smolinsky, and J. M. Andrews, J. Electrochem. Soc. 136, 1440-1446 (1989).

39. “A Self Aligned CoSi2 Source/Drain/Gate Multi-Gigahertz Symmetric CMOS Technology,” by S. J. Hillenius, H.-I. Cong, J. Lebowitz, J. M. Andrews, R. L. Field, L. Manchanda, W. S. Lindenberger, D. M. Boulin, and W. T. Lynch, Proc. Second International Symposium on ULSI Science and Technology PV 89-9, pp. 51-57, C. M. Osburn and J. M. Andrews, eds., Electrochem. Soc., Pennington, NJ (1989).

40. “Crystal Defects and Gettering for ULSI Yield Improvement,” by J. M. Andrews, Proc. I Brazilian Microelectronics School, Caxambu, MG, Mar. 5-9, 1990, pp. 283-319, Sociedade Brasileira de Microeletronica, Sao Paulo, SP, Brazil (1990).

41. “ULSI Metallization Technology,” by John Andrews, Proc. I Brazilian Microelectronics School, Caxambu, MG, Mar. 5-9, 1990, pp. 320-365, Sociedade Brasileira de Microeletronica, Sao Paulo, SP, Brazil (1990).

42. “Dielectric Breakdown Strength Analysis of SiO2 Using a Stepped-Field Testing Method,” by E. A. Sprangle, J. M. Andrews, and M. C. Peckerar, Proc. Third International Symposium on ULSI Science and Technology PV 91-11, pp. 409-420, J. M. Andrews and G. K. Celler, eds., Electrochem. Soc., Pennington, NJ (1991).

43. “Patterning Tungsten Films with an Electron Beam Lithography System at 50 keV for X-Ray Mask Applications,” K. W. Rhee, A. C. Ting, L. M. Shirey, K. W. Foster, J. M. Andrews, and M. C. Peckerar, J. Vac. Sci. Technol. (1991).

44. “Effects of Hydrogen Annealing on MOS Oxides,” by N. S. Saks and J. M. Andrews, Proc. Third Workshop on Radiation-Induced and/or Process-Related Electrically Active Defects in Semiconductor-Insulator Systems, Sept. 10-13, 1991, Microelectronics Center of North Carolina, Research Triangle Park, NC (1991).

45. "Effects of Hydrogen Annealing on MOS Oxides," by N. S. Saks and J. M. Andrews, J. Electron. Mater. 21, 775-780 (1992).

46. "Dielectric Breakdown Strength of SiO2 Using a Stepped-Field Method," by E. A. Sprangle, J. M. Andrews, and M. C. Peckerar, J. Electrochem. Soc. 139, 2617-2620 (1992).

47. "Elevated Temperature Nitrogen Implants in 6H-SiC," by Jason Gardner, Mulpuri V. Rao, O. W. Holland, G Kelner, David S. Simons, Peter H. Chi, John M. Andrews, J. Kretchmer, and M. Ghezzo, J. Electron. Mater. 25, 885-892 (1996).